1. Field of the Invention
The present invention relates to a semiconductor memory device including a non-volatile memory cell.
2. Description of Related Art
A MONOS (Metal Oxide Nitride Oxide Semiconductor) transistor is a kind of a non-volatile memory cell (see Eli Lusky et al. [2002], “Electron Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric.” IEEE Electron Device Letters, vol. 23, No. 9., which will be hereinafter referred to as “Non-patent Document 1”). In the MONOS transistor, diffusion layers 102a and 102b serving as source/drain regions are formed on the two outer sides of a part of a semiconductor substrate 101 which is a channel region, and a gate electrode 104 is formed above the part of the semiconductor substrate 101 which is the channel region with a gate insulating film 103 interposed between the gate electrode 104 and the channel region (see FIG. 7). The gate insulating film 103 is a laminated layer (ONO layer) obtained by superposing a silicon oxide film 103a, a silicon nitride film 103b and a silicon oxide film 103c in this sequence, and is formed to be level with the channel region. In a case where a write operation is performed on this MONOS transistor, predetermined voltages are applied to the semiconductor substrate 101, the gate electrode 104, the diffusion layers 102a and 102b. Thereby, electrons are trapped in a trap region 105 mainly in a vicinity of a boundary between the drain (the diffusion layer 102a or the diffusion layer 102b) and the channel region in the silicon nitride film 103b. 
The MONOS transistor described in Non-patent Document 1 has a structure which enables the silicon nitride film 103b to trap electrons throughout its entire surface opposite to the channel region. For this reason, if the MONOS transistor is miniaturized too much, one trap region 105 in a vicinity of the source region and another trap region 105 in a vicinity of the drain region are constructed too close to each other, and the trapped electrons accordingly interfere with one another. This brings about a problem that the reliability deteriorates. In addition, parts of the trapped electrons diffuse in directions in which the channel region extends (in the right and left directions in the figure) due to heat and the like. As a result, density of trapped electrons in the trap regions 105 becomes lower (in a later stage) when a time has passed since a write operation than (in an earlier stage) immediately after the write operation. This leads to fluctuation of the threshold value. This fluctuation brings about a disadvantage that the long-term reliability deteriorates (see FIG. 8).
For the purpose of compensating the disadvantage, Japanese Patent Application Laid-open Publication No. 2003-332474 (hereinafter referred to as “Patent Document 1”) has disclosed a semiconductor memory device characterized by including: a semiconductor substrate 211; a gate insulating film 212 formed on the semiconductor substrate 211; a single-layered gate electrode 213 formed on the gate insulating film 212; two charge retaining parts 261 and 262 formed at the two sides of a side wall of the single-layered gate electrode 213; two diffusion regions 217 and 218 corresponding to the charge retaining parts 261 and 262, respectively; and a channel region arranged under the single-layered gate electrode 213. The semiconductor memory device is also characterized in that each of the charge retaining parts 261 and 262 has a structure in which a silicon nitride film 215 for accumulating electrons is interposed between silicon oxide films 214 and 216. The charge retaining parts 261 and 262 are configured to change an amount of electric current which is going from the diffusion region 217 to the diffusion region 218, according to an amount of electrons retained in the silicon nitride film 215, when a voltage is applied to the gate electrode 213 (see FIG. 9). However, this semiconductor memory device has a disadvantage that a gate voltage controlling characteristic deteriorates in the trap region so that an electric current driving capability needed for fast readout cannot be sufficiently exerted. This is because the semiconductor memory device has a structure in which the gate electrode 213 does not overlap the trap regions (offset regions 242).
For the purpose of pursuing the miniaturization and preventing the electric current driving capability from deteriorating, Japanese Patent Application Laid-open Publication No. 2004-88055 (hereinafter referred to as “Patent Document 2) has disclosed a semiconductor device characterized by including an MIS transistor including: a semiconductor substrate 310 with a trench TR1 in its surface; a source region 311s formed in the semiconductor substrate 310 in a way that the source region 311s faces the surface of the semiconductor substrate 310; a drain region 311d formed in the semiconductor substrate 310 so as to face the surface of the semiconductor substrate 310, and to be away from the source region 311s with the trench TR1 interposed in between; a gate insulating film 320 formed on a portion interposed between the source region 311s and the drain region 311d so as to enter the trench TR1; and a gate electrode 330 formed on the gate insulating film 320 so as to enter the trench TR1. The semiconductor memory device is also characterized in that a first and second charge retaining parts capable of retaining charges CH1 and CH2, respectively, are formed in the gate insulating film 320 with the trench TR1 interposed between the first and second charge retaining parts (see FIG. 10). By forming the channel region into a concave shape, the semiconductor memory device is intended to be miniaturized, and to prevent the electric current driving capability from deteriorating. Nevertheless, the length LG of the channel is so long that the semiconductor memory device is not suitable for fast readout. In addition, density of trapped electrons can not be prevented from decreasing in the charge retaining parts (trap regions) due to heat or the like. This brings about a disadvantage that the threshold voltage fluctuates to a large extent.